Open Access

Simon Brunner

• The Fast Average Current Mode control methodology is a novel method for the implementation of a current compensator in a switched-mode power supply. It does not require compensation against sub-harmonic instability and is inductor independent. In this work, the digital implementation of this topology is compared against an analog implementation using simulation. Additionally, a hardware prototype is created to validate the digital simulation's results. In a Simulink environment, parameters of the digital implementation, such as the digital-to-analog converter resolutions and the delay counter frequency are varied to research their impact on system performance. The simulations show that a digital current compensator has similar performance as an analog implementation when designed tailored to the application. When evaluating the whole control loop the digital system is inferior due to added delays caused by digital to analog conversion. By operating the Buck converter hardware implementation as a current source, the functionality of the current mode control implementation in a FPGA was proven. Voltage control cannot be validated due to hardware issues. Due to the successful simulation of the source code with a mixed signal model of the converter, it can be assumed that it is functional. Apart from performance, a digital implementation shows many benefits compared to an analog solution, such as configurability of control parameters and easy compensation of component variations and aging.